EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 216
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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7–12
Figure 7–6. Number of I/Os in Each Bank in EP3SL340 Devices in the 1760-pin FineLine BGA Package
Notes to
(1) All I/O pin counts include dedicated clock inputs pins. The pin count includes all general purpose I/O, dedicated clock pins, and dual-purpose
(2)
Stratix III I/O Structure
Stratix III Device Handbook, Volume 1
configuration pins. Dedicated configuration pins are not included in the pin count.
Figure 7–6
Figure
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
7–6:
The I/O element (IOE) in Stratix III devices contains a bi-directional I/O buffer and
I/O registers to support a complete embedded bi-directional single data rate or DDR
transfer. The IOEs are located in I/O blocks around the periphery of the Stratix III
device. There are up to four IOEs per row I/O block and four IOEs per column I/O
block. The row IOEs drive row, column, or direct link interconnects. The column IOEs
drive column interconnects.
The Stratix III bi-directional IOE also supports the following features:
■
■
■
■
■
■
■
■
Number
of I/Os
Programmable input delay
Programmable output-current strength
Programmable slew rate
Programmable output delay
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination with calibration
50
50
36
50
50
36
Name
Bank
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
EP3SL340
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
Bank 6A
Name
Bank
Chapter 7: Stratix III Device I/O Features
Number
of I/Os
50
36
50
50
36
50
© July 2010 Altera Corporation
(Note
Stratix III I/O Structure
1),
(2)
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