EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 84

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

4–4
Figure 4–1. Stratix III Byte-Enable Functional Waveform for M9K and M144K
Stratix III Device Handbook, Volume 1
current data: q (asynch)
don't care: q (asynch)
contents at a0
contents at a1
contents at a2
address
byteena
inclock
wren
data
1
1
XXXX
XX
MLABs support byte-enable via emulation. There will be increased logic utilization
when the byte-enables are emulated.
The default value for the byte-enable signals is high (enabled), in which case writing
is controlled only by the write enable signals. The byte-enable registers have no clear
port. When using parity bits on the M9K and M144K blocks, the byte-enable controls
all nine bits (eight bits of data plus one parity bit). When using parity bits on the
MLAB, the byte-enable controls all 10 bits in the widest mode.
Byte-enables operate in a one-hot fashion, with the LSB of the byteena signal
corresponding to the least significant byte of the data bus. For example, if you are
using a RAM block in ×18 mode, with byteena = 01, data[8..0] is enabled and
data[17..9] is disabled. Similarly, if byteena = 11, both data[8..0] and
data[17..9] are enabled. Byte-enables are active high.
You cannot use the byte-enable feature when using the ECC feature on M144K blocks.
Figure 4–1
control the operations of the M9K and M144K.
When a byte-enable bit is de-asserted during a write cycle, the corresponding data
byte output can appear as either a “don’t care” value or the current data at that
location. The output value for the masked byte is controllable via the Quartus II
software. When a byte-enable bit is asserted during a write cycle, the corresponding
data byte output also depends on the setting chosen in the Quartus II software.
an
FFFF
doutn
doutn
FFFF
shows how the write enable (wren) and byte-enable (byteena) signals
10
a0
FFFF
ABXX
ABFF
ABCD
01
a1
XXCD
FFCD
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
11
a2
ABCD
ABCD
ABFF
a0
FFCD
ABFF
ABFF
ABCD
a1
© May 2009 Altera Corporation
XXXX
XX
FFCD
FFCD
a2
Overview
ABCD
ABCD