EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 171

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Figure 6–21. External Clock Outputs for Left/Right PLLs
Notes to
(1) These clock output pins can be fed by any one of the C[6..0], m counters.
(2) The CLKOUT0p and CLKOUT0n pins are dual-purpose I/O pins that can be used as two single-ended outputs or one single-ended output and
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
© July 2010
one external feedback input pin.
Figure
Altera Corporation
f
6–21:
Each pin of a single-ended output pair can either be in-phase or 180-degrees
out-of-phase. The Quartus II software places the NOT gate in the design into the IOE
to implement 180-degrees phase with respect to the other pin in the pair. The clock
output pin pairs support the same I/O standards as standard output pins (in the top
and bottom banks) as well as LVDS, LVPECL, differential HSTL, and differential
SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
Stratix III PLLs can also drive out to any regular I/O pin through the global or
regional clock network. You can use the external clock output pins as user I/O pins if
external PLL clocking is not needed.
LEFT/RIGHT
PLL_<L2, L3, R2, R3>_FB_CLKOUT0p (1), (2)
PLLs
Stratix III Device I/O Features
clkena0 (3)
m(fbout)
clkena1 (3)
C0
C1
C2
C3
C4
C5
C6
PLL_<L2, L3, R2, R3>_FB_CLKOUT0n (1), (2)
chapter.
Internal Logic
Stratix III Device Handbook, Volume 1
6–23