EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 431

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

© March 2010 Altera Corporation
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This chapter describes how to use the error detection cyclical redundancy check
(CRC) feature when a Stratix
errors. The purpose of the error detection CRC feature is to detect a flip in any of the
configuration CRAM bits in Stratix III devices due to a soft error. By using the error
detection circuitry, you can continuously verify the integrity of the configuration
CRAM bits.
In critical applications such as avionics, telecommunications, system control, and
military applications, it is important to be able to do the following:
■
■
The error detection feature has been enhanced in the Stratix III device family. In
addition, the error detection and recovery time for single event upset (SEU) in
Stratix III devices is reduced compared to Stratix II devices.
For Stratix III devices, use of the error detection CRC feature is provided in the
Quartus
Stratix III devices only support the error detection CRC feature at 1.1 V for V
feature is not supported in Stratix III devices operating at 0.9 V for V
Dedicated circuitry is built into Stratix III devices and consists of a CRC error
detection feature that can optionally check for SEUs continuously and automatically.
This section describes how to activate and use the error detection CRC feature when
your Stratix III device is in user mode and describes how to recover from
configuration errors caused by CRC errors.
Information about SEU is located on the Products page of the Altera
www.altera.com.
For more information regarding the test methodology for the enhanced error
detection in Stratix III, refer to
using CRC in Altera FPGA
For more information, refer to the
Paper.
Using CRC error detection for the Stratix III family has no impact on fitting or
performance of your device.
Confirm that the configuration data stored in a Stratix III device is correct.
Alert the system to the occurrence of a configuration error.
®
II software version 6.1 and onwards.
15. SEU Mitigation in Stratix III Devices
Devices.
®
III device is in user mode and recovers from CRC
AN 539: Test Methodology of Error Detection and Recovery
Robust SEU Mitigation with Stratix III FPGAs White
Stratix III Device Handbook, Volume 1
®
CCL
website at
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CCL
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