EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 233
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 7: Stratix III Device I/O Features
OCT Calibration
Figure 7–16. Example of Sharing Multiple I/O Banks with One OCT Calibration Block
Note to
(1)
OCT Calibration Block Modes of Operation
© July 2010
Figure 7–16
Figure
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
Altera Corporation
7–16:
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
Sharing an OCT Calibration Block in Multiple I/O Banks
An OCT calibration block has the same V
OCT R
standards, up to the number of available OCT calibration blocks. You can configure
I/O banks to receive calibrated codes from any OCT calibration block with the same
V
that particular I/O bank has an OCT calibration block.
For example,
voltage. If a group of I/O banks have the same V
calibration block to calibrate the group of I/O banks placed around the periphery.
Because 3B, 4C, 6C, and 7B have the same V
I/O banks (3B, 4C, 6C, and 7B) with the OCT calibration block located in bank 7A.
You can enable this by serially shifting out OCT R
calibration block located in bank 7A to the I/O banks located around the periphery.
Stratix III devices support calibration OCT R
calibration can occur in either power-up mode or user mode.
Power-Up Mode
In power-up mode, OCT calibration is automatically performed at power up and
calibrated codes are shifted to selected I/O buffers before transitioning to user mode.
CCIO
. All I/O banks with the same V
S
calibration is supported on all I/O banks with different V
Stratix III
Figure 7–16
shows a group of I/O banks that have the same V
Bank 6A
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
CCIO
can share one OCT calibration block, even if
CCIO
CCIO
S
as the I/O bank that contains the block.
and OCT R
as bank 7A, you can calibrate all four
CCIO
S
calibration codes from the OCT
voltage, you can use one OCT
(Note 1)
I/O bank with the same V
I/O bank with different V
T
in all I/O banks. The
Stratix III Device Handbook, Volume 1
CCIO
voltage
CCIO
CCIO
CCIO
7–29
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