EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 320
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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9–26
Stratix III Device Handbook, Volume 1
Using Both Center Left/Right PLLs
Both center left/right PLLs can be used simultaneously to drive DPA-disabled
channels on upper and lower differential banks. Unlike DPA-enabled channels, the
center left/right PLLs can drive cross-banks. For example, the upper center left/right
PLL can drive the lower differential bank at the same time the lower center left/right
PLL is driving the upper differential bank and vice versa, as shown in
Figure 9–23. Both Center Left/Right PLLs Driving Cross-Bank DPA-Disabled Channels
Simultaneously
Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Left/Right PLL
Left/Right PLL
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
Reference
Reference
Center
Center
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
CLK
CLK
Differential Pin Placement Guidelines
© July 2010 Altera Corporation
Figure
9–23.
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