EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 170
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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6–22
Figure 6–20. External Clock Outputs for Top/Bottom PLLs
Notes to
(1) These clock output pins can be fed by any one of the C[9..0], m counters.
(2) The CLKOUT0p and CLKOUT0n pins can be either single-ended or differential clock outputs. CLKOUT1 and CLKOUT2 pins are dual-purpose
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Stratix III Device Handbook, Volume 1
I/O pins that can be used as two single-ended outputs, one differential external feedback input pin pair or one single-ended external feedback input
pin (CLKOUT1 only). CLKOUT3 and CLKOUT4 pins are two single-ended output pins.
Figure
Top/Bottom
PLLs
6–20:
PLL_<#>_CLKOUT0p (1), (2)
clkena0 (3)
clkena1 (3)
m(fbout)
Figure 6–20
Any of the output counters (C[9..0] on Top/Bottom PLLs and C[6..0] on
Left/Right PLLs) or the M counter can feed the dedicated external clock outputs, as
shown in
all output pins available from a given PLL.
Each Left/Right PLL supports two clock I/O pins, configured as either two
single-ended I/Os or one differential I/O pair. When using both pins as single-ended
I/Os, one of them can be the clock output while the other pin is the external feedback
input (FB) pin. Hence, Left/Right PLLs only support external feedback mode for
single-ended I/O standards.
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
Figure 6–20
PLL_<#>_CLKOUT0n (1), (2)
shows the clock I/O pins associated with Top/Bottom PLLs.
PLL_<#>_FBp/CLKOUT1 (1), (2)
and
clkena3 (3)
clkena2 (3)
Figure
6–21. Therefore, one counter or frequency can drive
PLL_<#>_FBn/CLKOUT2 (1), (2)
Chapter 6: Clock Networks and PLLs in Stratix III Devices
clkena4 (3)
clkena5 (3)
PLL_<#>_CLKOUT3
(1), (2)
© July 2010 Altera Corporation
PLL_<#>_CLKOUT4
PLLs in Stratix III Devices
(1), (2)
Internal Logic
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