EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 396

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

12–12
Quartus II Software Support
Stratix III Device Handbook, Volume 1
1
1
The user watchdog timer is a counter that counts down from the initial value loaded
into the remote system upgrade control register by the factory configuration. The
counter is 29-bits wide and has a maximum count value of 2
user watchdog timer value, specify only the most significant 12 bits. The granularity
of the timer setting is 2
10-MHz internal oscillator.
internal oscillator.
Table 12–6. 10-MHz Internal Oscillator Specifications
The user watchdog timer begins counting once the application configuration enters
device user mode. This timer must be periodically reloaded or reset by the application
configuration before the timer expires by asserting RU_nRSTIMER. If the application
configuration does not reload the user watchdog timer before the count expires, a
time-out signal is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user watchdog
timer status bit (Wd) in the remote system upgrade status register and reconfigures the
device by loading the factory configuration.
To allow remote system upgrade dedicated circuitry to reset the watchdog timer, you
must assert the RU_nRSTIMER signal active for a minimum of 250 ns. This is
equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE
megafunction high for a minimum of 250 ns.
The user watchdog timer is disabled during the configuration cycle of the device.
Errors during configuration are detected by the CRC engine. Also, the timer is
disabled for factory configurations. Functional errors should not exist in the factory
configuration since it is stored and validated during production and is never updated
remotely.
The user watchdog timer is disabled in factory configurations and during the
configuration cycle of the application configuration. It is enabled after the application
configuration enters user mode. If you do not wish to use the user watchdog timer
feature during application configuration user mode operation, turn this feature off by
setting Wd_en bit to 1’b0 in the update register during factory configuration user
mode operation.
The Quartus II software provides the flexibility to include the remote system upgrade
interface between the Stratix III device logic array and the dedicated circuitry,
generate configuration files for productions, and remote programming of the system
configuration memory.
The implementation of the ALTREMOTE_UPDATE megafunction option in the
Quartus II software is for the interface between the remote system upgrade circuitry
and the device logic array interface. Using the megafunction block instead of creating
your own logic saves design time and offers more efficient logic synthesis and device
implementation.
Minimum
5
15
cycles. The cycle time is based on the frequency of the
Table 12–6
Typical
6.5
specifies the operating range of the 10-MHz
Chapter 12: Remote System Upgrades with Stratix III Devices
Maximum
10
29
© March 2010 Altera Corporation
. When specifying the
Quartus II Software Support
MHz
Unit