EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 245

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Design Considerations
© July 2010
Altera Corporation
f
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix III device I/O bank
has one VREF pin feeding a common V
be used as a generic I/O pin and should be tied to V
have a single V
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards use the same
V
For performance reasons, voltage-referenced input standards use their own V
as the power source. This feature allows you to place voltage-referenced input signals
in an I/O bank with a V
pins in an I/O bank with a 2.5-V V
parallel OCT enabled requires the V
input standard.
Voltage-referenced bi-directional and output signals must be the same as the I/O
bank’s V
bank with a 2.5-V V
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both non-voltage-referenced and voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
For pin connection guidelines, refer to the
Guidelines.
REF
setting.
CCIO
voltage. For example, you can only place SSTL-2 output pins in an I/O
CCIO
voltage level and a single V
CCIO
.
CCIO
of 2.5 or below. For example, you can place HSTL-15 input
CCIO
CCIO
. However, voltage-referenced input with
REF
of the I/O bank to match the voltage of the
bus. If it is not used as a VREF pin, it cannot
Stratix III Device Family Pin Connection
REF
voltage level at a given time.
CCIO
CCIO
or GND. Each bank can only
and 0.75-V V
Stratix III Device Handbook, Volume 1
CCIO
and a 0.9-V V
REF
.
CCPD
REF
.
level
7–41