EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 241
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 7: Stratix III Device I/O Features
Termination Schemes for I/O Standards
© July 2010
Altera Corporation
Differential LVPECL
In Stratix III devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported by Stratix III
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when LVPECL common mode voltage of the output buffer is
higher than Stratix III LVPECL input common mode voltage.
AC coupled termination scheme. The 50-Ω resistors used at the receiver end are
external to the device.
DC-coupled LVPECL is supported if the driving device’s LVPECL output common
mode voltage is within the Stratix III LVPECL input buffer specification (see
Figure
Figure 7–25. LVPECL AC Coupled Termination
Note to
(1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA LVPECL transmitter is used.
Figure 7–26. LVPECL DC Coupled Termination
Note to
(1) The LVPECL DC-coupled termination is applicable only when an Altera FPGA LVPECL transmitter is used.
RSDS
The row I/O banks support RSDS output using true LVDS output buffers without an
external resistor network. The column I/O banks support RSDS output using two
single-ended output buffers with the external one- or three-resistor networks, as
shown in
Figure
Figure
7–26).
Output Buffer
Figure
Output Buffer
7–25:
7–26:
LVPECL
LVPECL
7–27.
0.1 F
0.1 F
Z
Z
Z
Z
O
O
O
O
= 50
= 50
= 50
= 50
(Note 1)
(Note 1)
V
ICM
100
50
50
LVPECL Input Buffer
LVPECL Input Buffer
Stratix III Device Handbook, Volume 1
Stratix III
Figure 7–25
Stratix III
shows the
7–37
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