EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 287
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 8: External Memory Interfaces in Stratix III Devices
Stratix III External Memory Interface Features
Delay Chain
© March 2010 Altera Corporation
The output path is designed to route combinatorial or registered single data rate
(SDR) outputs and full-rate or half-rate DDR outputs from the FPGA core. Half-rate
data is converted to full-rate using the HDR block and is clocked by the half-rate clock
from the PLL. Resynchronization registers are also clocked by the same 0° system
clock, except in the DDR3 SDRAM interface where the leveling registers are clocked
by the write-leveling clock.
For more information about the write leveling delay chain, refer to
Circuitry”
The output-enable path has structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. You also have the resynchronization registers
similar to the output path registers structure, ensuring that the output-enable path
goes through the same delay and latency as the output path.
Stratix III devices have run-time adjustable delay chains in the I/O blocks and the
DQS logic blocks. You can control the delay chain setting through the I/O or the DQS
configuration block output.
Figure 8–22. Delay Chain
Every I/O block contains the following:
■
■
■
■
Two delay chains in series between the output registers and output buffer
One delay chain between the input buffer and input register
Two delay chains between the output enable and output buffer
Two delay chains between the OCT R
on
datain
page
8–31.
delayctrlin [3..0]
Figure 8–22
Δt
shows the delay chain ports.
T
enable control register and output buffer
finedelayctrlin
Δt
<use finedelayctrlin>
Stratix III Device Handbook, Volume 1
0
1
dataout
“Leveling
8–39
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