EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 107

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Introduction
DSP Block Overview
© March 2010 Altera Corporation
SIII51005-1.7
The Stratix
processing (DSP) blocks optimized for DSP applications. These DSP blocks of the
Altera
silicon blocks dedicated to maximizing signal processing capability, ease of use, and
lowest silicon cost.
Many complex systems such as WiMAX, 3GPP WCDMA, high-performance
computing (HPC), voice over Internet protocol (VoIP), H.264 video compression,
medical imaging, and HDTV use sophisticated digital signal processing techniques,
and this typically requires a large number of mathematical computations. Stratix III
devices are ideally suited as the DSP blocks consist of a combination of dedicated
elements that perform multiplication, addition, subtraction, accumulation,
summation, and dynamic shift operations. Along with the high-performance
Stratix III soft logic fabric and TriMatrix™ memory structures, you can configure
these blocks to build sophisticated fixed-point and floating-point arithmetic functions.
These can be manipulated easily to implement common larger computationally
intensive subsystems such as finite impulse response (FIR) filters, complex FIR filters,
infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and
discrete cosine transform (DCT) functions.
Each Stratix III device has two to seven columns of DSP blocks that implement
multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift
functions efficiently. The logical functionality of the Stratix III DSP block is a superset
of the previous generation of the DSP block found in Stratix and Stratix II devices.
Architectural highlights of the Stratix III DSP block include:
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High-performance, power-optimized, fully registered and pipelined
multiplication operations
Natively supported 9-bit, 12-bit, 18-bit, and 36-bit wordlengths
Natively supported 18-bit complex multiplications
Efficiently supported floating-point arithmetic formats (24-bit for single precision
and 53-bit for double precision)
Signed and unsigned input support
Built-in addition, subtraction, and accumulation units to combine multiplication
results efficiently
Cascading 18-bit input bus to form tap-delay line for filtering applications
Cascading 44-bit output bus to propagate output results from one block to the next
block without external logic support
Rich and flexible arithmetic rounding and saturation units
®
Stratix device family are the third generation of hardwired, fixed function
®
III family of devices have dedicated high-performance digital signal
5. DSP Blocks in Stratix III Devices
Stratix III Device Handbook, Volume 1