EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 363

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Figure 11–15. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V
(2) The
© March 2011 Altera Corporation
meet the V
(MAX II Device or
nCEO
Figure
Microprocessor)
External Host
ADDR
IH
Memory
pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
f
11–15:
specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with V
1
DATA0
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (maximum of 100 μs). After all
nSTATUS pins are released and pulled high, the MAX II device can attempt to
reconfigure the chain without needing to pulse nCONFIG low. If this option is turned
off, the MAX II device must generate a low-to-high transition (with a low pulse of at
least 2 μs) on nCONFIG to restart the configuration process.
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices will start
and complete configuration at the same time.
configuration when both Stratix III devices are receiving the same configuration data.
You can use a single configuration chain to configure Stratix III devices with other
Altera devices. To ensure that all devices in the chain complete configuration at the
same time, or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
Configuration Handbook.
V CCPGM (1)
10 k
Ω
V CCPGM (1)
10 k
GND
Ω
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix III Device
Configuring Mixed Altera FPGA Chains
MSEL2
MSEL1
MSEL0
nCEO
N.C.
GND
V
(2)
CCPGM
Figure 11–15
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix III Device
Stratix III Device Handbook, Volume 1
shows multi-device PS
CCPGM
STATUS
MSEL2
MSEL1
MSEL0
nCEO
must be high enough to
specification.
chapter in the
N.C.
CCPGM
GND
(2)
V
CCPGM
.
11–31