EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 141

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Application Examples
Table 5–10. DSP Block Dynamic Signals (Part 2 of 2)
Application Examples
FIR Example
© March 2010 Altera Corporation
ena0
ena1
ena2
ena3
aclr0
aclr1
aclr2
aclr3
Signal Name
—
A finite impulse response filter is a common function used in many systems to
perform spectral manipulations. The basic form is shown in
Equation 5–6. Finite Impulse Response Filter Equation
In this equation, x(n) is the input samples to the filter, c(k) are the filter coefficients,
and y(n) are the filtered output samples. Typically, the coefficients do not change in
time in most applications such as Digital Down Converters (DDC). FIR filters can be
implemented in many forms, the most simple being the tap-delay line approach.
Stratix III DSP block can implement various types of FIR filters very efficiently. To
form the tap-delay line, the input register stage of the DSP block has the ability to
cascade the input in a chained fashion in 18-bit wide format. Unlike the Stratix II DSP
block, which has two built-in parallel input register scan paths, Stratix III supports
only one built-in 18-bit parallel input register scan path for 288 data input.
For a pair of 18-bit input buses, the A input for the first 18-bit bus is fed back to be
registered again at the input of the second (lower) pair of inputs. Refer to
for details.
The B input of the multiplier feeds from the general routing. You can scan in the data
in 18-bit parallel form and multiply it by the 18-bit input bus from general routing in
each cycle.
Input and Pipeline Register enable signals
DSP block-wide asynchronous clear signals (active low).
Total Count per Full Block
y(n)
Function
=
N 1
k
∑
=
–
0
x n k
(
–
)
×
c k ( )
Stratix III Device Handbook, Volume 1
Equation
5–6.
Figure 5–22
Count
34
4
4
5–35