EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 286

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Figure 8–21. Stratix III IOE Output and Output-Enable Path Registers
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface.
(3) Half-rate and alignment clocks come from the PLL.
(4) These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.
(5) The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.
From Core (wdata2) (2)
From Core (wdata3) (2)
From Core (wdata0) (2)
From Core (wdata1) (2)
Half-Rate Clock (3)
Figure
From Core (2)
From Core (2)
8–21:
Half Data Rate to Single Data Rate Output-Enable Registers
D
D
D
D
D
D
DFF
DFF
Half Data Rate to Single Data Rate Output Registers
DFF
DFF
DFF
DFF
Q
Q
Q
Q
Q
Q
Alignment
D
D
D
Clock (3)
DFF
DFF
DFF
Q
Q
Q
0
1
0
1
0
1
D
D
D
(Note 1)
DFF
DFF
DFF
Q
Q
Q
D
D
D
DFF
DFF
DFF
Q
Q
Q
D
Alignment Registers (4)
Alignment Registers (4)
D
D
DFF
DFF
DFF
Q
Q
Q
Clock (5)
Write
DFF
DFF
Double Data Rate Output-Enable Registers
Output Reg Ao
Output Reg Bo
OE Reg A
DFF
OE Reg B
DFF
D
D
D
D
Double Data Rate Output Registers
Q
Q
Q
Q
OE
OE
1
0
1
0
OR2
TRI
DQ or DQS