EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 19

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

List of Figures
xix
Figure 9–14: LVDS/DPA Clocks with Center and Corner PLLs for Stratix III Devices . . . . . . . . . . . . . . 9-14
Figure 9–15: Bit Orientation in Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Figure 9–16: Bit-Order and Word Boundary for One Differential Channel
(Note 1)
. . . . . . . . . . . . . . . . 9-16
Figure 9–17: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA . . . . . . . . . . . 9-18
Figure 9–18: Corner and Center Left/Right PLLs Driving DPA-Enabled Differential I/Os in the Same Bank
9-20
Figure 9–19: Center Left/Right PLLs Driving DPA-Enabled Differential I/Os . . . . . . . . . . . . . . . . . . . . . 9-21
Figure 9–20: Invalid Placement of DPA-Enabled Differential I/Os Driven by Both Center Left/Right PLLs
9-22
Figure 9–21: Corner and Center Left/Right PLLs Driving DPA-Disabled Differential I/Os in the Same Bank
9-24
Figure 9–22: Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven
by the Corner and Center Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Figure 9–23: Both Center Left/Right PLLs Driving Cross-Bank DPA-Disabled Channels Simultaneously .
9-26
Figure 10–1: Hot-Socketing Circuitry for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Figure 10–2: Transistor Level Diagram of a Stratix III Device I/O Buffers . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Figure 10–3: Simplified POR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Figure 11–1: Enabling Compression for Stratix III Bitstreams in Compiler Settings . . . . . . . . . . . . . . . . . 11-5
Figure 11–2: Compressed and Uncompressed Configuration Data in the Same Configuration File . . . 11-6
Figure 11–3: Single Device FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Figure 11–4: Multi-Device FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Figure 11–5: Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the
Same Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Figure 11–6: FPP Configuration Timing Waveform
(Note
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Figure 11–7: FPP Configuration Timing Waveform with Decompression or Design Security Feature En-
abled
(Note
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Figure 11–8: Single Device Fast AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Figure 11–9: Multi-Device Fast AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Figure 11–10: Multi-Device Fast AS Configuration When the Devices Receive the Same Data Using a Single
SOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Figure 11–11: Fast AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Figure 11–12: In-System Programming of Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
Figure 11–13: Single Device PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
Figure 11–14: Multi-Device PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
Figure 11–15: Multiple-Device PS Configuration When Both Devices Receive the Same Data . . . . . . . 11-31
Figure 11–16: PS Configuration Timing Waveform
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
Figure 11–17: PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
Figure 11–18: Multi-Device PS Configuration using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36
Figure 11–19: JTAG Configuration of a Single Device Using a Download Cable . . . . . . . . . . . . . . . . . . 11-39
Figure 11–20: JTAG Configuration of Multiple Devices Using a Download Cable . . . . . . . . . . . . . . . . . 11-41
Figure 11–21: JTAG Configuration of a Single Device Using a Microprocessor . . . . . . . . . . . . . . . . . . . . 11-42
Figure 12–1: Functional Diagram of Stratix III Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Figure 12–2: Remote System Upgrade Block Diagram for Stratix III Fast AS Configuration Scheme . . 12-2
Figure 12–3: Enabling Remote Update for Stratix III Devices in Compiler Settings . . . . . . . . . . . . . . . . . 12-4
Figure 12–4: Transitions Between Configurations in Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . 12-6
Figure 12–5: Remote System Upgrade Circuit Data Path
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Figure 12–6: Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Figure 12–7: Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Figure 12–8: Interface Signals Between the ALTREMOTE_UPDATE Megafunction and the Nios II Proces-
© March 2011 Altera Corporation
Stratix III Device Handbook, Volume 1