LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 88

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop

controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock

circuitry is used. For this device XCLKS is mapped to PE7.

The XCLKS signal selects the oscillator conﬁguration during reset low phase while a clock quality check

is ongoing. This is the case for:

The selected oscillator conﬁguration is frozen with the rising edge of the RESET pin in any of these above

described reset cases.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Power on reset or low-voltage reset

Clock monitor reset

Any reset while in self-clock mode or full stop mode

Oscillator Conﬁguration

Figure 1-10. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)

Figure 1-11. Full Swing Pierce Oscillator Connections (XCLKS = 0)

Figure 1-12. External Clock Connections (XCLKS = 0)

MC9S12XE-Family Reference Manual , Rev. 1.23

Not Connected

speciﬁed by crystal vendor

Ceramic Resonator

CMOS-Compatible

External Oscillator

Ceramic Resonator

Freescale Semiconductor