LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1238

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Appendix A Electrical Characteristics

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing

the PORF bit in the CRG ﬂags register has not been set.

When external reset is asserted for a time greater than PW

reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an

oscillation before reset.

Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is

performed before releasing the clocks to the system.

If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and

SCME = 1), the system will resume operation in self-clock mode after t

The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both

modes. The controller can be woken up by internal or external interrupts. After t

the interrupt vector.

SRAM Data Retention

External Reset

Stop Recovery

Pseudo Stop and Wait Recovery

is out of speciﬁcation limits, the SRAM contents integrity is guaranteed if after the reset

MC9S12XE-Family Reference Manual , Rev. 1.23

the CRG module generates an internal

the CPU starts fetching

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