LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 730

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)
20.3.2.1
Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until
SCIBDL is written to as well, following a write to SCIBDH.
Write: Anytime, if AMAP = 0.
The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared
modulation/demodulation submodule.
730
Module Base + 0x0000
Module Base + 0x0001
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SBR[12:0]
TNP[1:0]
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
IREN
Field
6:5
4:0
7:0
7
W
W
R
R
SBR7
IREN
Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.
0 IR disabled
1 IR enabled
Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow
pulse. See
SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is
calculated two different ways depending on the state of the IREN bit.
The formulas for calculating the baud rate are:
Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the
Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in
SCI Baud Rate Registers (SCIBDH, SCIBDL)
0
0
7
7
When IREN = 0 then,
When IREN = 1 then,
Those two registers are only visible in the memory map if AMAP = 0 (reset
condition).
SCI baud rate = SCI bus clock / (16 x SBR[12:0])
SCI baud rate = SCI bus clock / (32 x SBR[12:1])
first time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and
IREN = 1).
a temporary location until SCIBDL is written to.
Table
TNP1
SBR6
0
0
6
6
20-3.
Table 20-2. SCIBDH and SCIBDL Field Descriptions
Figure 20-3. SCI Baud Rate Register (SCIBDH)
Figure 20-4. SCI Baud Rate Register (SCIBDL)
MC9S12XE-Family Reference Manual , Rev. 1.23
SBR5
TNP0
5
0
5
0
SBR12
SBR4
NOTE
0
0
4
4
Description
SBR11
SBR3
0
0
3
3
SBR10
SBR2
2
0
2
1
Freescale Semiconductor
SBR9
SBR1
0
0
1
1
SBR8
SBR0
0
0
0
0