LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 232

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 4 Memory Protection Unit (S12XMPUV1)

access is allowed or represents an access violation. If an access violation caused by the S12X CPU is

detected, the MPU module raises an access violation interrupt. If the MPU module detects an access

violation caused by a bus master other than the S12X CPU, it ﬂags an access error condition to the

respective master. In addition to the restrictions deﬁned for memory ranges in the MPU descriptors,

accesses to memory not covered by any MPU descriptor (even read accesses!) are considered access

1. Master 3 can be implemented or left out depending the chip conﬁguration. Please refer to the Device Reference Manual for

information about the availability and function of Master 3.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Protects memory from undesired accesses coming from up to 3 bus masters

Eight memory protection descriptors

— each descriptor can cover the full global memory map (8 MBytes)

— each descriptor has a granularity of 8 Bytes

Op-code Fetch

Op-code Fetch

shows a block diagram of the MPU module.

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 4-1. Block Diagram

Access Validation

MPU Monitoring

Access Violation

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