LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 190

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 2 Port Integration Module (S12XEPIMV1)

Figure 2-109. Pulse Illustration

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4

consecutive samples of an active level directly or indirectly.

The ﬁlters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock

is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC

oscillator runs only if the following condition is true on any pin individually:

Sample count <= 4 and interrupt enabled (PIE=1) and interrupt ﬂag not set (PIF=0)

Initialization Information

Port Data and Data Direction Register writes

It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins

from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor