LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 762

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)

The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the

RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.

The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single

wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative

status register 1. This ﬂag is also cleared if the bit error detect feature is disabled.

The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the

SCIASR1 SCI alternative status register 1. This ﬂag is also cleared if break detect feature is disabled.

The SCI interrupt request can be used to bring the CPU out of wait mode.

An active edge on the receive input can be used to bring the CPU out of stop mode.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Recovery from Wait Mode

Recovery from Stop Mode

RXEDGIF Description

BERRIF Description

BKDIF Description

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor