LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 268

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 6 Interrupt (S12XINTV2)

The XINT module has no external signals.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Interrupt Requests

External Signal Description

(Up to 108 Channels)

shows a block diagram of the XINT module.

One Set Per Channel

Block Diagram

To XGATE Module

Non I Bit Maskable

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 6-1. XINT Block Diagram

INT_XGPRIO = XGATE Interrupt Priority

= bits from the channel conﬁguration

in the associated conﬁguration register

XGATE Request Route,

Priority Level

= Interrupt Vector Base

= Interrupt Processing Level

Freescale Semiconductor