LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 174

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.94
2.3.95
174
Address 0x0371
Address 0x0372
Write:Never, writes to this register have no effect.
Write: Anytime.
DDRL
Field
Field
PTIL
Reset
Reset
7-0
7-0
W
W
R
R
Port L input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port L data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port L pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRL7
PTIL7
Port L Input Register (PTIL)
Port L Data Direction Register (DDRL)
u
0
7
7
= Unimplemented or Reserved
DDRL6
PTIL6
u
0
6
6
Figure 2-93. Port L Data Direction Register (DDRL)
Table 2-90. DDRL Register Field Descriptions
Table 2-89. PTIL Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-92. Port L Input Register (PTIL)
DDRL5
PTIL5
u
0
5
5
DDRL4
PTIL4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRL3
PTIL3
3
u
3
0
DDRL2
PTIL2
u
0
2
2
Access: User read/write
Freescale Semiconductor
DDRL1
PTIL1
u
0
1
1
Access: User read
DDRL0
PTIL0
u
0
0
0
(1)
(1)