LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 153

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
2.3.61
Freescale Semiconductor
Function
Address 0x0268
Write: Anytime.
Altern.
Field
Reset
PTJ
PTJ
PTJ
PTJ
7-6
5-4
3
2
W
R
(TXCAN0)
Port J general purpose input/output data—Data Register
Port J pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN4 and the routed CAN0, as well as with
SCL and SDA signals of IIC0, respectively.
The CAN4 function takes precedence over the IIC0, the routed CAN0 and the general purpose I/O function if the
CAN4 module is enabled. The IIC0 function takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured as
open drain outputs. The routed CAN0 function takes precedence over the general purpose I/O function if the routed
CAN0 module is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data Register
This pin is associated with the SCL and SDA signals of IIC1, and with chip select outputs CS2 and CS0, respectively.
The IIC1 function takes precedence over the chip select and general purpose I/O function if the IIC1 is enabled. The
chip selects take precedence over the general purpose I/O. If the IIC1 module takes precedence the SDA1 and SCL1
outputs are configured as open drain outputs. Refer to IIC section for details.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data Register
This pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data Register
This pin is associated with the chip select output signal CS2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
TXCAN4
SCL0
PTJ7
Port J Data Register (PTJ)
0
7
(RXCAN0)
RXCAN4
SDA0
PTJ6
0
6
Table 2-57. PTJ Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-59. Port J Data Register (PTJ)
SCL1
PTJ5
CS2
—
0
5
SDA1
PTJ4
CS0
—
0
4
Description
PTJ3
—
—
—
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PTJ2
CS1
—
—
0
2
Access: User read/write
TXD2
PTJ1
—
—
0
1
RXD2
PTJ0
CS3
—
0
0
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