LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 476

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)

The REFDV register provides a ﬁner granularity for the IPLL multiplier steps.

Read: Anytime

Write: Anytime except when PLLSEL = 1

The REFFRQ[1:0] bit are used to conﬁgure the internal PLL ﬁlter for optimal stability and lock time. For

correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK

frequency as shown in

IPLL (no locking and/or insufﬁcient stability).

The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the

ﬁnal divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f

(divide by one).

Module Base + 0x0001

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

S12XECRG Reference Divider Register (REFDV)

S12XECRG Post Divider Register (POSTDIV)

Write to this register initializes the lock detector bit.

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Figure 11-4. S12XECRG Reference Divider Register (REFDV)

Table 11-3. Reference Clock Frequency Selection

11-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional

REFCLK Frequency Ranges

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor