LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 818

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 23 Voltage Regulator (S12VREGL3V3V1)

REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

3. Shutdown mode

Controlled by VREGEN (see device level speciﬁcation for connectivity of VREGEN).

This mode is characterized by minimum power consumption. The regulator outputs are in a high-

impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API

internal RC oscillator clock is not available.

This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the

VREG_3V3 to use external supplies.

Block Diagram

shows the function principle of VREG_3V3 by means of a block diagram. The regulator core

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor