LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 722

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)

Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by

the low order CAEx bit. The high order CAEx bit has no effect.

or center aligned) and 8-bit (normal) or 16-bit (concatenation).

The reset state of each individual bit is listed within the

details the registers and their bit-ﬁelds. All special functions or modes which are initialized during or just

following reset are described within this section.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

The 8-bit up/down counter is conﬁgured as an up counter out of reset.

All the channels are disabled and all the counters do not count.

is used to summarize which channels are used to set the various control bits when in 16-bit

summarizes the boundary conditions for the PWM regardless of the output mode (left aligned

1. Counter = $00 and does not count.

PWM Boundary Cases

(indicates no duty)

Table 19-5. 16-bit Concatenation Mode Summary

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 19-6. PWM Boundary Cases

(indicates no period)

Section 19.3.2, “Register Descriptions”

Freescale Semiconductor