LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 433

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LDB
Operation
M[RB, #OFFS5]
M[RB, RI]
M[RB, RI]
RI-1
Loads a byte from memory into the low byte of register RD. The high byte is cleared.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
LDB RD, (RB, #OFFS5)
LDB RD, (RS, RI)
LDB RD, (RS, RI+)
LDB RD, (RS, -RI)
—
N
1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H
Not affected.
Not affected.
Not affected.
Not affected.
—
Z
—
V
Source Form
—
C
⇒ RD.L;
⇒ RD.L;
⇒ RD.L;
⇒ RI;
MC9S12XE-Family Reference Manual Rev. 1.23
$00
$00
$00
M[RS, RI] ⇒ RD.L;
Address
Mode
IDO5
IDR+
-IDR
IDR
Load Byte from Memory
⇒ RD.H
⇒ RD.H
⇒ RD.H;
0
0
0
0
(Low Byte)
1
1
1
1
0
1
1
1
0
0
0
0
RI+1 ⇒ RI;
$00 ⇒ RD.H
0
0
0
0
Machine Code
RD
RD
RD
RD
1
RB
RB
RB
RB
Chapter 10 XGATE (S12XGATEV3)
RI
RI
RI
OFFS5
LDB
0
0
1
0
1
0
Cycles
Pr
Pr
Pr
Pr
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