LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 454

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
STW
Operation
RS ⇒ M[RB, #OFFS5]
RS ⇒ M[RB, RI]
RS ⇒ M[RB, RI];
RI–2 ⇒ RI;
Stores the content of register RS to memory.
CCR Effects
Code and CPU Cycles
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
454
N:
Z:
V:
C:
STW RS, (RB, #OFFS5)
STW RS, (RB, RI)
STW RS, (RB, RI+)
STW RS, (RB, -RI)
—
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Not affected.
Not affected.
Not affected.
Not affected.
—
Z
—
V
Source Form
—
C
RI+2 ⇒ RI;
RS ⇒ M[RB, RI]
MC9S12XE-Family Reference Manual , Rev. 1.23
Address
Mode
IDO5
IDR+
-IDR
IDR
Store Word to Memory
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
Machine Code
RS
RS
RS
RS
RB
RB
RB
RB
RI
RI
RI
Freescale Semiconductor
OFFS5
STW
0
0
1
0
1
0
Cycles
PW
PW
PW
PW