LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 727

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
20.1.4
Figure 20-1
blocks.
Freescale Semiconductor
RXD Data In
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Bus Clock
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Block Diagram
is a high level block diagram of the SCI module, showing the interaction of various function
Baud Rate
Generator
Decoder
Infrared
1/16
MC9S12XE-Family Reference Manual Rev. 1.23
Transmit Shift Register
Receive Shift Register
Data Format Control
Figure 20-1. SCI Block Diagram
Receive & Wakeup
SCI Data Register
SCI Data Register
Transmit Control
Control
Chapter 20 Serial Communication Interface (S12SCIV5)
Generation
Generation
Interrupt
Transmit
Interrupt
Encoder
Receive
Infrared
RXEDG
IDLE
RDRF/OR
BRKD
BERR
TDRE
TC
Data Out TXD
Interrupt
Request
SCI
727

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