LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 699

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts
off for power savings.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0000
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PWME7
PWME6
PWME5
PWME4
PWME3
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7
6
5
4
3
W
R
PWME7
Pulse Width Channel 7 Enable
0 Pulse width channel 7 is disabled.
1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when
Pulse Width Channel 6 Enable
0 Pulse width channel 6 is disabled.
1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when
Pulse Width Channel 5 Enable
0 Pulse width channel 5 is disabled.
1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when
Pulse Width Channel 4 Enable
0 Pulse width channel 4 is disabled.
1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
0
7
The first PWM cycle after enabling the channel can be irregular.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled.
its clock source begins its next cycle.
PWME6
0
6
Figure 19-3. PWM Enable Register (PWME)
MC9S12XE-Family Reference Manual Rev. 1.23
PWME5
5
0
PWME4
NOTE
0
4
Description
PWME3
0
3
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
PWME2
2
0
PWME1
0
1
PWME0
0
0
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