LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 172

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.93
172
Function
Address 0x0370
PTRRR
PTRRR
PTRRR
PTRRR
PTRRR
PTRRR
Write: Anytime.
Altern.
Field
Reset
5
4
3
2
1
0
W
R
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC5 is available on PP5
0 TIMIOC5 is available on PR5
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC4 is available on PP4
0 TIMIOC4 is available on PR4
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC3 is available on PP3
0 TIMIOC3 is available on PR3
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC2 is available on PP2
0 TIMIOC2 is available on PR2
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC1 is available on PP1
0 TIMIOC1 is available on PR1
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC0 is available on PP0
0 TIMIOC0 is available on PR0
(TXD7)
PTL7
Port L Data Register (PTL)
0
7
Table 2-87. PTR Routing Register Field Descriptions (continued)
(RXD7)
PTLT6
0
6
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-91. Port L Data Register (PTL)
(TXD6)
PTL5
0
5
(RXD6)
PTL4
0
4
Description
(TXD5)
PTL3
3
0
(RXD5)
PTL2
0
2
Access: User read/write
Freescale Semiconductor
(TXD4)
PTL1
0
1
(RXD4)
PTL0
0
0
(1)