LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 473

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

This section lists and describes the signals that connect off chip.

These pins provides operating voltage (V

the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required V

RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a

known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Signal Description

must be connected to properly.

MC9S12XE-Family Reference Manual Rev. 1.23

Figure 11-1. Block diagram of S12XECRG

Illegal Address Reset

Power on Reset

Low Voltage Reset

) and ground (V

Clock and Reset Control

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)

Clock Quality

) for the IPLL circuitry. This allows

System Reset

Oscillator Clock

Real Time Interrupt

PLL Lock Interrupt

Self Clock Mode