LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 302

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Background Debug Module (S12XBDMV2)
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then
ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data
has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See
Section 7.4.3, “BDM Hardware Commands”
for more information on the BDM commands.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
(Target MCU)
Drives SYNC
To BKGD Pin
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
Target MCU
BDM Clock
BKGD Pin
BKGD Pin
Drives to
ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst
case delay time at the appropriate places in the protocol.
Host
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
Figure 7-14. ACK Pulse and SYNC Request Conflict
Host SYNC Request Pulse
MC9S12XE-Family Reference Manual , Rev. 1.23
ACK Pulse
16 Cycles
Host and
Target Drive
to BKGD Pin
At Least 128 Cycles
and
NOTE
Section 7.4.4, “Standard BDM Firmware Commands”
Electrical Conflict
High-Impedance
Freescale Semiconductor
Speedup Pulse