LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 403

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BFFO
Operation
FirstOne(RS) ⇒ RD;
Searches the first “1” in register RS (from MSB to LSB) and writes the bit position into the destination
register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be
cleared and the carry flag will be set. This is used to distinguish a “1” in position 0 versus no “1” in the
whole RS register at all.
CCR Effects
1. Before executing the instruction
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
BFFO RD, RS
0
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
0; cleared.
Set if the result is $0000; cleared otherwise.
0; cleared.
Set if RS = $0000
∆
Z
0
V
Source Form
∆
C
(1)
; cleared otherwise.
MC9S12XE-Family Reference Manual Rev. 1.23
Address
Mode
DYA
Bit Field Find First One
0
0
0
0
1
Machine Code
RD
RS
Chapter 10 XGATE (S12XGATEV3)
1
0
BFFO
0
0
0
Cycles
P
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