LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 133

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

1. Read: Always reads 0x00

Freescale Semiconductor

Address 0x024E

Address 0x024F

Write: Anytime.

Write: Unimplemented

Port S wired-or mode—Enable wired-or functionality

This register conﬁgures the output pins as wired-or independent of the function used on the pins. If enabled the

output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of

several serial modules. These bits have no inﬂuence on pins used as inputs.

1 Output buffers operate as open-drain outputs.

0 Output buffers operate as push-pull outputs.

Port S Wired-Or Mode Register (WOMS)

PIM Reserved Register

= Unimplemented or Reserved

Figure 2-33. Port S Wired-Or Mode Register (WOMS)

Table 2-32. WOMS Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 2-34. PIM Reserved Register

u = Unaffected by reset

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write

Access: User read