LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 556

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime
Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a
zero will not affect the current status of the bit.
556
Module Base + 0x0027
MCPR[1:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
MCEN
Reset
ICLAT
FLMC
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
1:0
4
3
2
W
R
MCZF
Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3
and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse
accumulators will be automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will always return zero.
Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus
down-counter is enabled (MCEN = 1).
A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets
the modulus counter prescaler.
Write zero to this bit has no effect. Read of this bit will return always zero.
Modulus Down-Counter Enable
0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early
1 Modulus counter is enabled.
Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler
when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of
the load register into the modulus counter count register occurs.
0
7
interrupt flag when the modulus down-counter is enabled.
Figure 14-43. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
= Unimplemented or Reserved
0
0
MCPR1
6
Table 14-23. MCCTL Field Descriptions (continued)
0
0
1
1
Table 14-24. Modulus Counter Prescaler Select
MC9S12XE-Family Reference Manual Rev. 1.23
5
0
0
MCPR0
0
1
0
1
0
0
4
Description
Prescaler Division
POLF3
0
3
16
1
4
8
POLF2
2
0
Freescale Semiconductor
POLF1
0
1
POLF0
0
0