LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 143

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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1. Read: Anytime.

Freescale Semiconductor

Address 0x025A

Write: Anytime.

Port P input data—

This register always reads back the buffered state of the associated pins. This can also be used to detect overload

or short circuit conditions on output pins.

Port P data direction—

This register controls the data direction of pin 7.

The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin

is forced to be an input. In these cases the data direction bit will not change.

1 Associated pin is conﬁgured as output.

0 Associated pin is conﬁgured as input.

Port P data direction—

The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this

case the data direction bit will not change.

1 Associated pin is conﬁgured as output.

0 Associated pin is conﬁgured as input.

Port P Data Direction Register (DDRP)

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on PTP or PTIP registers, when changing the

DDRP register.

Figure 2-45. Port P Data Direction Register (DDRP)

Table 2-43. DDRP Register Field Descriptions

Table 2-42. PTIP Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write

LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 143

LFEBS12UB

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