LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 512

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)

ETRIGCH[3:0]

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

1. Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means

external trigger source is still on one of the AD channels selected by ETRIGCH3-0

Discharge Before Sampling Bit

0 No discharge before sampling.

1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to

External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs

as source for the external trigger. The coding is summarized in

the sampling time. This can help to detect an open circuit instead of measuring the previous sampled

Table 13-4. ATDCTL1 Field Descriptions (continued)

Table 13-6. External Trigger Channel Select Coding

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 13-5. A/D Resolution Coding

A/D Resolution

External trigger source is

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