LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 688

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)

Read: Anytime

Write: Has no meaning or effect

Module Base + 0x000A, 0x000B

Module Base + 0x000E, 0x000F

Module Base + 0x0012, 0x0013

Module Base + 0x0016, 0x0017

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the

PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer

has counted down to zero the PTF time-out ﬂag will be set and the register value will be loaded. The PFLT bits

in the PITFLT register can be used to immediately update the count register with the new value if an immediate

load is desired.

PIT Count Register 0 to 3 (PITCNT0–3)

Figure 18-15. PIT Count Register 0 (PITCNT0)

Figure 18-16. PIT Count Register 1 (PITCNT1)

Figure 18-17. PIT Count Register 2 (PITCNT2)

Figure 18-18. PIT Count Register 3 (PITCNT3)

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 18-9. PITLD0–3 Field Descriptions

Freescale Semiconductor