LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1126

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)
28.4.2.13 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of a specific P-Flash or D-Flash block.
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set User Margin Level command are defined in
1126
FERSTAT
Register
FSTAT
CCOBIX[2:0]
Table 28-57. Set User Margin Level Command FCCOB Requirements
Table 28-56. Verify Backdoor Access Key Command Error Handling
000
001
MGSTAT1
MGSTAT0
EPVIOLIF
ACCERR
Error Bit
FPVIOL
1. Read margin to the erased state
2. Read margin to the programmed state
(CCOBIX=001)
Table 28-58. Valid Set User Margin Level Settings
0x0000
0x0001
0x0002
CCOB
MC9S12XE-Family Reference Manual , Rev. 1.23
Set if CCOBIX[2:0] != 100 at command launch
Set if a Load Data Field command sequence is currently active
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section
Set if the backdoor key has mismatched since the last reset
None
None
None
None
0x0D
28.3.2.2)
Return to Normal Level
User Margin-1 Level
User Margin-0 Level
FCCOB Parameters
Margin level setting
Level Description
Global address [22:16] to identify the
Error Condition
(1)
(2)
Flash block
Table
Freescale Semiconductor
28-58.