LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 127

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
2.3.24
2.3.25
Freescale Semiconductor
Address 0x0243
Address 0x0244
Write: Anytime.
Write: Anytime.
RDRT
PERT
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port T reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port T pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
RDRT7
PERT7
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTT or PTIT registers, when changing the
DDRT register.
RDRT6
PERT6
Figure 2-23. Port T Pull Device Enable Register (PERT)
0
0
6
6
Figure 2-22. Port T Reduced Drive Register (RDRT)
Table 2-23. RDRT Register Field Descriptions
Table 2-24. PERT Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
RDRT5
PERT5
0
0
5
5
RDRT4
PERT4
NOTE
0
0
4
4
Description
Description
RDRT3
PERT3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
RDRT2
PERT2
0
0
2
2
Access: User read/write
Access: User read/write
RDRT1
PERT1
0
0
1
1
RDRT0
PERT0
0
0
0
0
127
(1)
(1)