LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 585

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
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SDA
SCL
Table
IBC5-3
(bin)
000
001
010
011
100
101
110
111
15-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used
Table
15-4, all subsequent tap points are separated by 2
MC9S12XE-Family Reference Manual Rev. 1.23
scl2start
Table 15-5. Prescale Divider Encoding
(clocks)
126
14
30
62
2
2
2
6
Table 15-6. Multiplier Factor
IBC7-6
00
01
10
11
scl2stop
(clocks)
SCL Divider
129
17
33
65
7
7
9
9
RESERVED
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MUL
01
02
04
(clocks)
scl2tap
126
14
30
62
4
4
6
6
SDA Hold
(clocks)
tap2tap
IBC5-3
128
Table
16
32
64
1
2
4
8
as shown in the
15-6.
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