LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 790

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 22 Timer Module (TIM16B8CV2) Block Description
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
22.1.1
The TIM16B8CV2 includes these distinctive features:
22.1.2
Stop:
Freeze:
Wait:
Normal:
790
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Eight input capture/output compare channels.
Clock prescaling.
16-bit counter.
16-bit pulse accumulator.
Features
Modes of Operation
Timer is off because clocks are stopped.
Timer counter keep on running, unless TSFRZ in TSCR1 (0x0006) is set to 1.
Counters keep on running, unless TSWAI in TSCR1 (0x0006) is set to 1.
Timer counter keep on running, unless TEN in TSCR1 (0x0006) is cleared to 0.
MC9S12XE-Family Reference Manual Rev. 1.23
Freescale Semiconductor

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