LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 613

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

This section describes in detail all the registers and register bits in the MSCAN module. Each description

includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld

function follow the register diagrams, in bit order. All bits of all registers in this module are completely

synchronous to internal clocks during a register read.

The CANCTL0 register provides various control bits of the MSCAN module as described below.

Freescale Semiconductor

Module Base + 0x0000

0x001C–0x001F

0x0018–0x001B

0x0020–0x002F

0x0030–0x003F

0x0010–0x0013

0x0014–0x0017

MSCAN Control Register 0 (CANCTL0)

= Unimplemented

Figure 16-3. MSCAN Register Summary (continued)

Figure 16-4. MSCAN Control Register 0 (CANCTL0)

MC9S12XE-Family Reference Manual Rev. 1.23

= Unimplemented or Reserved

Section 16.3.3, “Programmer’s Model of Message

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Access: User read/write