LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 144

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x025B

Address 0x025C

Write: Anytime.

Port P reduced drive—Select reduced drive for outputs

This register conﬁgures the drive strength of output pins 7 through 0 as either full or reduced independent of the

function used on the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port P pull device enable—Enable pull devices on input pins

These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect

if the pin is used as an output. Out of reset no pull device is enabled.

1 Pull device enabled.

0 Pull device disabled.

Port P Reduced Drive Register (RDRP)

Port P Pull Device Enable Register (PERP)

Figure 2-47. Port P Pull Device Enable Register (PERP)

Figure 2-46. Port P Reduced Drive Register (RDRP)

Table 2-44. RDRP Register Field Descriptions

Table 2-45. PERP Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor