LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 144

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.48
2.3.49
144
Address 0x025B
Address 0x025C
Write: Anytime.
Write: Anytime.
RDRP
PERP
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port P reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port P pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
RDRP7
PPSP7
Port P Reduced Drive Register (RDRP)
Port P Pull Device Enable Register (PERP)
0
0
7
7
RDRP6
PPSP6
Figure 2-47. Port P Pull Device Enable Register (PERP)
0
0
6
6
Figure 2-46. Port P Reduced Drive Register (RDRP)
Table 2-44. RDRP Register Field Descriptions
Table 2-45. PERP Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
RDRP5
PPSP5
0
0
5
5
RDRP4
PPSP4
0
0
4
4
Description
Description
RDRP3
PPSP3
3
0
3
0
RDRP2
PPSP2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
RDRP1
PPSP1
0
0
1
1
RDRP0
PPSP0
0
0
0
0
(1)
(1)

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