LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 178

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Port Integration Module (S12XEPIMV1)
178
Field
PTF
PTF
PTF
PTF
PTF
PTF
PTF
PTF
7
6
5
4
3
2
1
0
Port F general purpose input/output data—Data Register
Port F pin 7 is associated with the TXD signal of the SCI3 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 6 is associated with the RXD signal of the SCI3 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 5 is associated with the TXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 4 is associated with the RXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 3 is associated with the TXD signal of the SC5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 2 is associated with the RXD signal of the SCI5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Table 2-96. PTF Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Description
Freescale Semiconductor