LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 145

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Freescale Semiconductor

Address 0x025D

Address 0x025E

Write: Anytime.

Read: Anytime.

Port P pull device select—Determine pull device polarity on input pins

This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-

up or pull-down device if enabled.

1 A rising edge on the associated Port P pin sets the associated ﬂag bit in the PIFP register. A pull-down device is

0 A falling edge on the associated Port P pin sets the associated ﬂag bit in the PIFP register.A pull-up device is

Port P interrupt enable—

This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P.

1 Interrupt is enabled.

0 Interrupt is disabled (interrupt ﬂag masked).

Port P Polarity Select Register (PPSP)

Port P Interrupt Enable Register (PIEP)

connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used

connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used

Figure 2-49. Port P Interrupt Enable Register (PIEP)

Figure 2-48. Port P Polarity Select Register (PPSP)

Table 2-46. PPSP Register Field Descriptions

Table 2-47. PPSP Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write