LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 827

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The period can be calculated as follows depending of APICLK:
23.3.2.6
The Reserved 06 is reserved for test purposes.
23.3.2.7
The VREGHTTR register allows to trim the VREG temperature sense.
Freescale Semiconductor
0x02F6
0x02F7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Fiption
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
HTTR[3:0]
HTOEN
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
3–0
7
W
W
R
R
Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period
HTOEN
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
Reserved 06
High Temperature Trimming Register (VREGHTTR)
High Temperature Trimming Bits — See
0
0
0
7
7
1. When trimmed within specified accuracy. See electrical specifications for details.
Table 23-9. Selectable Autonomous Periodical Interrupt Periods (continued)
APICLK
= Unimplemented or Reserved
= Unimplemented or Reserved
1
HTTR[3]
0
0
0
0
6
6
Bit
MC9S12XE-Family Reference Manual Rev. 1.23
Table 23-10. VREGHTTR field descriptions
Increases V
APIR[15:0]
5
0
0
5
0
0
FFFF
Table 23-11. Trimming Effect
Figure 23-8. Reserved 06
Figure 23-9. VREGHTTR
HT
twice of HTTR[2]
Table 23-11
0
0
0
0
4
4
Trimming Effect
Description
for trimming effects.
HTTR3
131072 * bus clock period
0
0
0
3
3
1
Selected Period
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
HTTR2
0
2
0
0
2
1
HTTR1
0
0
0
1
1
1
HTTR0
0
0
0
0
0
1
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